1. Field of Invention
The present invention relates to a phase-locked loop compiler. More particularly, the present invention relates to a digital phase-locked loop compiler.
2. Description of Related Art
FIG. 1 is a block diagram showing a conventional analog phase-locked loop device. A conventional analog phase-locked loop device, comprises: a divider 102, 112, and 114, a phase-frequency detector 104, a comparator 106, a low pass filter 108, and a voltage control oscillator 110. The signal of a conventional analog phase-locked loop is analog and therefore phase-locking must be achieved through continuous adjustment of the analog signal. Hence, the phase-locking time is longer. Furthermore, the low-pass filter in a conventional analog phase-locked device often occupies as much as 80% of the area. With the filter occupying such a large area, it is inconvenient to add other circuits such as a built-in self-tester (BIST) around the phase-lock loop. In brief, a conventional analog phase-locked loop has the following disadvantages:                1. Latch-up time of the analog phase-locked loop is too long.        2. A low-pass filter that occupies too much of the available surface area is required.        3. The incorporation of a BIST and other circuits on the phase-locked loop device is difficult.        